1. Field of the Invention
The present invention relates to a field effect transistor with reduced capacitive coupling between drain and substrate.
2. Description of the Related Art
For numerous large signal applications, LDMOS transistors or LDMOS field effect transistors (LDMOS=lateral diffused metal oxide semiconductor) are used, such as for power amplifiers for base stations, hand sets, mobile telephones, etc. The output capacity of a LDMOS field effect transistor is dependent on the drain voltage or the voltage between the drain or the drain area on the one hand and the substrate often connected with a reference potential on the other.
FIG. 3 is a schematic illustration of a vertical section through a conventional LDMOS field effect transistor. A p-doped base substrate 10 comprises a first lower surface 12 and a second upper surface 14. At the lower surface 12, the base substrate 10 comprises a backside contact in the form of a metal coating 16. On the other surface 14 of the base substrate 10 a p-doped epitaxial layer 20 is created by means of an epitaxial method, such as by means of CVD epitaxy (CVD=chemical vapor deposition). The base substrate 10 and the epitaxial layer 20 together form a device substrate 30 with a surface 32 that is at the same time a surface of the epitaxial layer 20 facing away from the base substrate 10.
In or on the epitaxial layer 20, a field effect transistor or its semiconductor function elements are arranged. A source area 40 is formed by an n+-doped area at or directly below the surface 32. A p-doped enhance area 42 borders the side of the source area 40 facing away from the surface 32. A p-doped body area 44, which has, however, in contrast to the enhance area 42, a greater expansion than the source area 40 in at least one direction and thus also laterally borders the source area 40 and the enhance area 42 as well as the surface 32, borders a side of the enhance area 42 facing away from the source area 40 and the surface 32.
A drain area, which is formed from free drain sub-areas 50, 52, 54 with differently high doping concentration in this embodiment, is arranged on the surface 32, laterally spaced from the source area 40 but laterally bordering the body area 44. A first drain sub-area 50 having the greatest distance to the source area 40 is n+-doped. In direction to the source area 40, a second drain sub-area 52 whose doping concentration is lower than that of the first drain sub-area 50 borders the first drain sub-area 50. A third drain sub-area 54 bordering the body area 44 and having a lower doping concentration than the second drain sub-area 52 borders the second drain sub-area 52. The second drain sub-area 52 and the third drain sub-area 54 together are also called resurf area (resurf=reduced surface field).
A p+-doped area 60 on the surface 32 borders a side of the source area 40 facing away from the drain area 50, 52, 54. Between the p+-doped area 60 and the base substrate 10 or its upper surface 14, a p-doped sinker 62 extends that increases the electric conductivity between the p+-doped area 60 and the base substrate 10.
At a side of the p+-doped area 60 and the sinker 62 facing away from the source area 40, the enhance area 42, and the body area 44, further structures 40′, 42′, 44′ border laterally, which are for example a further source area, a further enhance area, and a further body area, or the source area 40, enhance area 42, and the body area 44 that are laterally guided around the p+-doped area 60 and the sinker 62 in the form of an open or closed arc or frame.
On the epitaxial layer 20, electrically conductive structures from metals or other electric conductors are arranged embedded in a dielectric layer 66. A source metallization 70 borders the source area 40 and the p+-doped area 60 and contacts them or is connected thereto in an electrically conductive manner. Throughhole conductors 72 connect the source metallization 70 to shielding conductors 74 overlapping laterally or being arranged partly vertically above the source metallization 70 and being part of an overlying metallization plane in an electrically conductive manner.
A drain metallization 80 borders the most highly doped first drain sub-area 50 and is connected thereto in an electrically conductive manner.
Above the portion of the body area 54 bordering the surface 32, a gate 90 from a doped polysilicon layer 92 and a silicide layer 94 is arranged. The gate 90 or the polysilicon layer 92 thereof is spatially spaced and electrically insulated from the surface 32 or the body area 44 substantially opposite the gate 90 by a thin insulating layer 96 (gate oxide).
When applying a positive voltage to the gate 90, a thin conductive layer, a so-called channel, forms in the body area 44 opposite gate 90 close to the surface 32. The area in which the channel forms when applying the positive voltage is designated as channel area 98 in the following.
A pn-junction is present between the drain area 50, 52, 54 on the one hand and adjacent areas of the epitaxial layer 20 on the other. A space charge zone or a depletion zone forms there. The thickness or expansion of the space charge or depletion zone that is perpendicular to the pn-junction is dependent on the magnitude of the applied drain voltage or on a potential difference between the drain area 50, 52, 54 on the one hand and the substrate 10 on the other hand. The reverse-biased pn-junction between the drain area 50, 52, 54 and the substrate 10 at the same time forms a capacitor whose capacitance is dependent on the thickness of the mentioned space charge zone, and thus on the drain voltage.
As already mentioned above, the output capacitance, which is dependent on the drain voltage, or the capacitance between the drain area 50, 52, 54 and the substrate 10, complicates the matching of a circuit therewith, which is connected to the field effect transistor. Previously, this output capacitance of the field effect transistor, which is dependent on the drain voltage, had to be tolerated.